RTL Design & Integration Engineer (On-site. Bengaluru, India)

**RTL Design & Integration Engineer | SoC & ASIC Development

Build the next generation of ultra-low-power, brain-inspired compute systems powered by Wi-R.**

On-site – Bengaluru, India | Competitive salary + bonus + early equity

We provide comprehensive relocation support for engineers based outside Bengaluru.

About Ixana

Ixana is a Purdue University spinoff pioneering brain-inspired wearable computing. We've developed Wi-R, a patented communication tech that's 100x more energy-efficient than Bluetooth or Wi-Fi. Join our 60-person team building the next era of real-time, AI-powered human-computer interaction.

The Wi-R Revolution

Wi-R is our patented non-radiative near-field communication technology that creates secure "wire-like wireless" experiences through small E-field bubbles around your body. This breakthrough enables unprecedented energy efficiency at sub-0.1 nanojoules per bit, making long-term wearable and implantable devices finally practical.

See Wi-R in action: Visit [ixana.ai](http://ixana.ai) for demos of high-speed data streaming through skin contact: <https://vimeo.com/ixana/pairing-contact-transfer>

What You’ll Do

• Perform RTL integration of internal/external IPs and subsystems into top-level SoCs.
• Develop and maintain RTL wrappers, interconnect logic, and clock/reset infrastructures.
• Run lint, CDC, and early synthesis checks to ensure high-quality integration.
• Collaborate closely with design, verification, and physical design teams to ensure clean handoff.
• Debug simulation and synthesis issues at both block and chip levels.
• Maintain and automate integration flows using Python/Perl/Tcl.
• Contribute to design reviews and document integration flows.

What We're Looking For

Required:

• 2–6 years of experience in RTL design and SoC/IP integration.
• Strong RTL skills using Verilog/SystemVerilog.
• Experience with AXI/AHB/APB protocols and interconnect architectures.
• Hands-on experience with tools like Synopsys Design Compiler, Spyglass, or similar.
• Proficiency in scripting languages (Python, Perl, Tcl) for flow automation.
• Understanding of synthesis, timing, and SoC assembly flows.

Preferred:

• Exposure to UPF/CPF and low-power design methodologies.
• Experience with SoC integration frameworks and custom EDA automation.
• Familiarity with high-performance, low-power compute architectures.

Compensation & Benefits

• Competitive base salary aligned with experience
• Cash bonus + meaningful early-stage equity
• Relocation support, partner job-search assistance
• Medical, dental, vision coverage; generous PTO
• Inventor awards for patents and contributions

Why Join Us

• Work on cutting-edge deep tech that shapes the future of human-computer interaction
• Collaborate with world-class SoC, RF, mixed-signal, and wearable computing engineers
• Full ownership from architecture to silicon
• Fast-paced, transparent, and deeply technical culture
• Global exposure and opportunities to grow into lead roles

Ready to re‑wire the future of human-computer interaction?

Apply via our careers page. In your note, tell us how you envision using Wi‑R to transform everyday experiences across healthcare, industry, or consumer tech.

_Ixana is an equal opportunity employer committed to advancing human-computer interfaces through innovative low-power electronics innovation._

Keywords: RTL Design, SoC Integration, ASIC, Verilog, SystemVerilog, AXI, AHB, APB, Synthesis, Low-Power Design, UPF, EDA Automation, Python, Tcl, Digital Design, Startup, Human-Computer Interaction