EOSL_EDA Design Intern (S100/S200)

This internship is in ITRI's Electronics and Optoelectronics Systems Research Laboratories (EOSL).

Intern will work on the following topics / tasks:

AI-Driven EDA Development and Research

1. Develop fully automated parameter exploration and optimization algorithms and tools based on existing EDA platforms.

2. Design and implement 2.5D/3D chip layout algorithms with considerations for power, performance, and area (PPA).

3. Develop next-generation numerical analysis and computational solvers to accelerate convergence speed.

4. Develop generative programming-based IP and SoC verification technologies to improve verification efficiency and convergence.

Qualifications:

1. Major and student level: Master's or Ph.D. degree.

2. Required/desired background with specific skills (software, equipment, processes, etc.): Educational or research background relevant to AI-driven EDA, chip layout optimization, numerical analysis, or SoC/IP verification.

3. Language or other qualifications: Must be able to work on-site at the Hsinchu Zhongxing Campus.