CPU Architecture Verification Engineer

Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels — from Senior Engineer to Principal level — to help prove that the Nuvacore CPU is architecturally correct. As part of the design verification (DV) team, you will help drive architectural verification — checking the CPU's behavior and architectural state against the architecture specification and a golden reference model — building the stimulus, checkers, and flows that find architectural bugs long before silicon, working shoulder-to-shoulder with architecture and RTL design.

THE ROLE

Plan & Strategy: Drive the verification scope, strategy, and test plans for architectural correctness — the CPU's behavior and architectural state versus the specification and a golden reference model.

Environment Setup: Build, maintain, and scale robust verification environments — including co-simulation against the golden reference model — that compare architectural state end to end.

Test & Debug: Generate stimulus in assembly and random instruction sequences (RIS) to exercise the full instruction set and architectural corner cases such as exceptions, interrupts, and privilege transitions.

Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the architectural test plan is complete.

Cross-functional Collaboration: Partner with architects and RTL teams to root-cause mismatches across RTL, model, and specification, drive design fixes, and support emulation, FPGA, and silicon bring-up.

REQUIREMENTS — MUST TO HAVE

Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels — from Senior Engineer to Principal level — to help prove that the Nuvacore CPU is architecturally correct. As part of the design verification (DV) team, you will help drive architectural verification — checking the CPU's behavior and architectural state against the architecture specification and a golden reference model — building the stimulus, checkers, and flows that find architectural bugs long before silicon, working shoulder-to-shoulder with architecture and RTL design.

THE ROLE

Plan & Strategy: Drive the verification scope, strategy, and test plans for architectural correctness — the CPU's behavior and architectural state versus the specification and a golden reference model.

Environment Setup: Build, maintain, and scale robust verification environments — including co-simulation against the golden reference model — that compare architectural state end to end.

Test & Debug: Generate stimulus in assembly and random instruction sequences (RIS) to exercise the full instruction set and architectural corner cases such as exceptions, interrupts, and privilege transitions.

Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the architectural test plan is complete.

Cross-functional Collaboration: Partner with architects and RTL teams to root-cause mismatches across RTL, model, and specification, drive design fixes, and support emulation, FPGA, and silicon bring-up.

REQUIREMENTS — MUST TO HAVE